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MMDF2P02HD
Preferred Device
Power MOSFET 2 Amps, 20 Volts
P-Channel SO-8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients.
Features http://onsemi.com
2 AMPERES, 20 VOLTS RDS(on) = 160 mW
P-Channel D
G S
* * * * * * * * *
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive - Can Be Driven by Logic ICs Miniature SO-8 Surface Mount Package - Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for SO-8 Package Provided Pb-Free Package is Available
Rating Symbol VDSS VDGR VGS ID ID Value 20 20 20 3.3 2.1 20 2.0 - 55 to 150 324 Unit Vdc Vdc Vdc Adc Apk W C mJ
MARKING DIAGRAM
8 8 1 SO-8, DUAL CASE 751 STYLE 11 1 D2P02 AYWWG G
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1)
Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 MW) Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 ms) Total Power Dissipation, TA = 25C (Note 2) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 20 Vdc, VGS = 5.0 Vdc, IL = 6.0 Apk, L = 18 mH, RG = 25 W) Thermal Resistance, Junction-to-Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds
D2P02 = Device Code A = Assembly Location Y = Year WW = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
PIN ASSIGNMENT
Source-1 Gate-1 Source-2 Gate-2 1 2 3 4 8 7 6 5 Drain-1 Drain-1 Drain-2 Drain-2
IDM PD TJ, Tstg EAS
ORDERING INFORMATION
RqJA TL 62.5 260 C/W C Device MMDF2P02HDR2 MMDF2P02HDR2G Package SO-8 Shipping 2500 Tape & Reel
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Negative sign for P-Channel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.
(c) Semiconductor Components Industries, LLC, 2006
SO-8 2500 Tape & Reel (Pb-Free)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Preferred devices are recommended choices for future use and best overall value.
1
February, 2006 - Rev. 7
Publication Order Number: MMDF2P02HD/D
MMDF2P02HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3)
Characteristic OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 4) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 2.0 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, RG = 6.0 W) (VDS = 10 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc, RG = 6.0 W) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 4) (IS = 2.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD - - trr (VDD = 15 V, IS = 2.0 A, dIS/dt = 100 A/ms) ta tb QRR 3. Negative sign for P-Channel device omitted for clarity. 4. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%.max. 5. Switching characteristics are independent of operating junction temperature. - - - - 1.5 1.24 38 17 21 0.034 2.1 - - - - - mC ns Vdc - - - - - - - - - - - - 19 66 25 37 11 21 45 36 15 1.2 5.0 4.0 38 132 50 74 22 42 90 72 20 - - - nC ns (VDS = 16 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss - - - 420 290 116 588 406 232 pF VGS(th) 1.0 - RDS(on) - - gFS 2.0 0.118 0.152 3.0 0.160 0.180 - mhos 1.5 4.0 2.0 - Vdc mV/C W V(BR)DSS 20 - IDSS - - IGSS - - - - 1.0 10 100 nAdc - 25 - - Vdc mV/C mAdc Symbol Min Typ Max Unit
Reverse Recovery Time
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MMDF2P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
4 I D , DRAIN CURRENT (AMPS) 4 I D , DRAIN CURRENT (AMPS)
VGS = 10 V 4.5 V
3.9 V
3.7 V 3.5 V
TJ = 25C
VDS 10 V
3
3
3.3 V 2 3.1 V 1 2.9 V 2.7 V 2.5 V 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1.8 2
2
1 100C 0 1.0 TJ = - 55C 1.5 2.0 2.5 3.0 3.5 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 25C
Figure 1. On-Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.6
ID = 1 A TJ = 25C
0.20 TJ = 25C 0.16 VGS = 4.5 V
0.4
0.12
10 V
0.2
0.08
0 0 2 4 6 8 10 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
0.04 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance versus Gate-To-Source Voltage
Figure 4. On-Resistance versus Drain Current and Gate Voltage
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
1.6 VGS = 10 V ID = 2 A 1.4 I DSS, LEAKAGE (nA)
100
VGS = 0 V
TJ = 125C
1.2
10 100C
1.0
0.8
0.6 -50
- 25
0
25
50
75
100
125
150
1
0
5
10
15
20
TJ, JUNCTION TEMPERATURE (C)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
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MMDF2P02HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1200 1000 C, CAPACITANCE (pF) 800 600 Crss 400 200 0 10 Coss Crss 5 VGS 0 VDS 5 10 15 20 Ciss
The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
VDS = 0 V Ciss
VGS = 0 V
TJ = 25C
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)
Figure 7. Capacitance Variation
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MMDF2P02HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 VGS 8 6 4 Q1 2 Q3 0 0 4 VDS 8 12 QT, TOTAL GATE CHARGE (nC) Q2 ID = 2 A TJ = 25C 12 9 6 3 0 16 15 18 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000 VDD = 10 V ID = 2 A VGS = 10 V TJ = 25C t, TIME (ns)
100 td(off) tf tr 10 1 td(on) 10 RG, GATE RESISTANCE (OHMS) 100
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.
2.0 VGS = 0 V TJ = 25C I S , SOURCE CURRENT (AMPS) 1.6
1.2
0.8
0.4
0 0.5
0.7 0.9 1.1 1.3 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
1.5
Figure 10. Diode Forward Voltage versus Current http://onsemi.com
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MMDF2P02HD
di/dt = 300 A/ms I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RqJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C
E , SINGLE PULSE DRAIN-TO-SOURCE AS AVALANCHE ENERGY (mJ)
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.
350 ID = 6 A 300 250 200 150 100 50 0 25 50 75 100 125 150
10
100 ms 1 ms 10 ms
1
dc
0.1
RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100
0.01 0.1
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (C)
Figure 12. Maximum Rated Forward Biased Safe Operating Area
Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature
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MMDF2P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
1
D = 0.5 0.2 0.1 0.05 0.02 0.01
0.1
Normalized to qja at 10s.
Chip
0.0175 W 0.0710 W 0.2706 W 0.5776 W 0.7086 W
0.01 SINGLE PULSE 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
Ambient 1.0E+03
1.0E-01 t, TIME (s)
1.0E+00
1.0E+01
1.0E+02
Figure 14. Thermal Response
di/dt IS trr ta tb TIME tp 0.25 IS
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MMDF2P02HD
PACKAGE DIMENSIONS
SOIC-8 CASE 751-07 ISSUE AG
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
STYLE 11: PIN 1. 2. 3. 4. 5. 6. 7. 8.
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
MiniMOS are trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MMSF2P02HD/D

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